1. Field of the Invention
The present invention relates to amplifier circuits, and, more particularly, to an amplifier circuit suitable for a sense amplifier in a semiconductor memory device, for example.
2. Description of the Background Art
A sense amplifier is for amplifying a small potential difference on a bit line pair in a semiconductor memory device, and sense amplifiers having various circuit configurations having been developed so far.
FIG. 10 is a circuit diagram illustrating an example of a structure of a conventional sense amplifier disclosed in Japanese Patent Publication No. 1-55769 (1989), for example. Referring to FIG. 10, the sense amplifier includes load transistors 1, 3 and input transistors 2, 4. Each of load transistors 1, 3 is implemented with a P channel MOSFET. Each of input transistors 2, 4 is implemented with an N channel MOSFET. The source of each of load transistors 1, 3 is connected to a power supply (voltage Vcc). The drain of load transistor 1 is connected to the drain of input transistor 2, and the drain of load transistor 3 is connected to the drain of input transistor 4. Gates of load transistors 1, 3 are connected to each other and to the drain of input transistor 2. The source of each of input transistors 2, 4 is grounded. An input signal DIa is applied to the gate of input transistor 2, and an input signal DIb is applied to the gate of input transistor 4. Input signals DIa, DIb are supplied through a bit line pair, and they are complementary to each other. The sense amplifier illustrated in FIG. 10 amplifies the potential difference between input signal DIa and input signal DIb. An output terminal 7 is connected to the drain of input transistor 2. An output terminal 8 is connected to the drain of input transistor 4. An output signal DOa is obtained from output terminal 8, and an output signal DOb is obtained from output terminal 7.
Load transistor 1 and input transistor 2 constitute a first inverter. Load transistor 3 and input transistor 4 constitute a second inverter The conductance of load transistor 1 and the conductance of load transistor 3 are set to be equal, and the conductance of input transistor 2 and the conductance of input transistor 4 are set to be equal.
A current mirror-type CMOS amplifier circuit is implemented with the above-described structure.
Now, operation of the sense amplifier illustrated in FIG. 10 will be described with reference to FIGS. 11 and 12.
Referring to FIG. 11, when the voltage V.sub.5 of input signal DIa and the voltage V.sub.6 of input signal DIb are the same voltage Vr, the current characteristic of input transistor 2 is as represented by the solid line curve I.sub.2. The current characteristic of load transistor 1 is as represented by the solid line curve I.sub.1 because the drain and gate of load transistor 1 are short-circuited. The crossing point P.sub.0 of the solid line curves I.sub.2 and I.sub.1 represents the output voltage of the first inverter, i.e. the output voltage V.sub.7 of output signal DOb. The current characteristic of load transistor 3 is as represented by the solid line curve I.sub.3, and the current characteristic of input transistor 4 is as represented by the solid line curve I.sub.4 because the conductance of second inverter is set to be the same as the conductance of the first inverter, and the gate of load transistor 3 is connected to output terminal 7. Accordingly, the output voltage of the second inverter, i.e the output voltage V.sub.8 of output signal DOa is as represented by the crossing point P.sub.0 of the solid line curves I.sub.3 and I.sub.4, which is the same as the output voltage of the first inverter.
Next, consideration will be given to the case where complimentary signals are supplied as input to the sense amplifier illustrated in FIG. 10.
First, in the case where the voltage V.sub.5a of input signal DIa is Vr+.DELTA.Vr, and the voltage V.sub.6a of input signal DIb is Vr-.DELTA.Vr, the
characteristic curves shift from the solid line curve I.sub.2 to the dotted-line curve I.sub.2a, from the solid line curve I.sub.3 to the dotted-line curve I.sub.3a, and from the solid line curve I.sub.4 to the dotted-line curve I.sub.4a. Accordingly, the crossings of these curves shift from P.sub.0 to P.sub.1 and P.sub.2, and the output voltage of the second inverter, i.e. the output voltage V.sub.8a of output signal DOa, becomes a high voltage V.sub.H corresponding to the crossing point P.sub.2.
Conversely, in the case where the voltage V.sub.5b of input signal DIa is Vr-.DELTA.Vr, and the voltage V.sub.6b of input signal DIb is Vr+.DELTA.Vr, the characteristic curves shift from the solid line curve I.sub.2 to the dotted-line curve I.sub.2b, from the solid line curve I.sub.3 to the dotted-line curve I.sub.3b, and from the solid line curve I.sub.4 to the dotted-line curve I.sub.4b, respectively, as illustrated in FIG. 12. Accordingly, the crossing points of these characteristic curves shift from P.sub.0 to P.sub.3 and P.sub.4, and the output voltage of the second inverter, i.e. the output voltage V.sub.8b of output signal DOa becomes a low voltage V.sub.L corresponding to the crossing point P.sub.4.
As described above, the potential difference 2.DELTA.Vr between input signals DIa and DIb is amplified to be V.sub.E -V.sub.L. In the sense amplifier illustrated in FIG. 10, the current flowing in the first inverter and the current flowing in the second inverter are of the same intensity. Therefore, the sense amplifier illustrated in FIG. 10 is referred to as a current mirror-type CMOS amplifier circuit.
However, the amplifier circuit illustrated in FIG. 10 has an asymmetrical structure. Therefore, in the case where complementary signals are supplied as inputs to input transistors 2, 4, change in the output voltage V.sub.7 of the first inverter is extremely small as compared to change in the output voltage V.sub.8 of the second inverter. Specifically, the output voltage V.sub.7 of the first inverter changes only to the voltage V.sub.7a or V.sub.7b. As a result, an amplified output signal can be obtained only from the second inverter side in the amplifier circuit illustrated in FIG. 10, so that there was a problem that the gain is small.
In addition, the amplifier circuit illustrated in FIG. 10 has an asymmetrical structure, so that there was a problem that the offset voltage caused by diversification of the characteristics of elements constituting the circuit or the like is transmitted intact to the circuit in the next stage.
A CMOS sense amplifier having a symmetrical structure is disclosed in U.S. Pat. No. 4,479,202 for solving various problems as described above. FIG. 13 is a circuit diagram illustrating the structure of the sense amplifier illustrated in U.S. Pat. No. 4,479,202.
The CMOS sense amplifier illustrated in FIG. 13 includes load transistors 5 and 6 added to the structure of the CMOS sense amplifier illustrated in FIG. 10. Each of load transistors 5, 6 is implemented with a P channel MOSFET. The source of each of load transistors 5, 6 is connected to a power supply in the same manner as load transistors 1, 3. The drain of load transistor 5 is connected to the drain of input transistor 2, and the drain of load transistor 6 is connected to the drain of input transistor 4. The gates of load transistors 5, 6 are connected to each other and to the drain of input transistor 4. Load transistors 1, 5 and input transistor 2 constitute a first inverter, and load transistors 3, 6 and input transistor 4 constitute a second inverter.
Load transistors 1, 3, 5, and 6 are set to have equal conductance, and input transistors 2, 4 are also set to have equal conductance.
Now, operation of the CMOS sense amplifier illustrated in FIG. 13 will be described.
When the potentials of input signals DIa and DIb are equal, it is clear that the potentials of output signals DOa, DOb are also equal, since load transistors 1, 3, 5, and 6 have equal conductance and input transistors 2, 4 have equal conductance.
In the case where complementary input signals DIa, DIb (DIa&gt;Dib) are applied to the gates of input transistors 2, 4, the potentials of output signals DOa, DOb are going to be changed by the functions of load-transistors 1, 3. The rise in potential of output signal DOa acts to reduce the conductivity of load transistor 5. Therefore, in the first inverter, the conductivity of input transistor 2 becomes relatively high, and the potential of output signal DOb is made lower. In addition, the fall in the potential of output signal DOb acts to increase the conductivity of load transistor 3. Consequently, the potential of output signal DOa is made higher.
In the case where the relationship between the potentials of input signals DIa, DIb applied to the gates of input transistors 2, 4 is reverse to the above-described one (DIa&lt;DIb), an operation exactly reverse to the above-described one is carried out in the circuit, since the sense amplifier illustrated in FIG. 13 has a symmetrical structure. Specifically, the potential of output signal DOa is lowered greatly, and the potential of output signal DOb is raised greatly.
As described above, the sense amplifier illustrated in FIG. 13 has a symmetrical structure, so that fluctuation of the potentials of both output signals DOa, DOb is large. Therefore, it is possible to provide an amplifier circuit having a larger gain as compared to that of the sense amplifier illustrated in FIG. 10.
As described above, the sense amplifier illustrated in FIG. 13 has a symmetrical structure, so that it has a large gain and a small offset voltage. However, there is a danger of an undesired through current flowing from the power supply to ground when operation is unnecessary (in a period during which the sense amplifier should be rendered inactive) in the sense amplifier illustrated in FIG. 13. Specifically, in the case where one of or both of input signals DIa, DIb attain(s) a value exceeding the threshold voltage of input transistors 2, 4 for any reason when operation is unnecessary, one of or both of input transistors 2, 4 turn(s) on. This causes one or both of load transistors 1, 3 to turn on, and a current path is formed from the power supply toward ground. A through current flows in the current path. Accordingly, the problem with the amplifier circuit illustrated in FIG. 13 was that there is a danger of current flowing even when operation is unnecessary, and current consumption becomes large.
While the sense amplifier illustrated in FIG. 13 is improved so that a larger gain is obtained as compared to that of the sense amplifier illustrated in FIG. 10, there was a demand for realizing a further larger gain.